A 36-bit Balanced Moduli MAC Architecture

Recently a renewed interest is seen in RNS (Residue Number System) which stems out from the fact that these systems are inherently parallel and modular and thus are fast and simple. In many DSP applications Multiply-Accumulate (MAC) operation turns out to be the most basic one and hence an RNS based 36-bit MAC architecture is presented in this paper to speed up the whole operation. A further enhancement in speed up is achieved by exploiting the logarithmic properties of Galois fields and integer rings. The choice of forward and reverse converters used in the design results in considerable savings in silicon real estate. The adder cells used is based on pass transistor design which attribute to very low power consumption.